As one type of an analog-to-digital (A/D) converter, an A/D converter called a cyclic type or an algorithmic type is known. A configuration of a general cyclic A/D converter is disclosed in, for example, JP-A-2008-28820.
This A/D converter includes an analog-to-digital (A/D) converting circuit, a digital-to-analog (D/A) converting circuit, an amplifier circuit, an input difference circuit, and two switches. The A/D converting circuit converts an input analog signal into a digital signal. The D/A converting circuit converts an output of the A/D converting circuit into an analog signal. The amplifier circuit amplifies an input analog signal. In JP-A-2008-28820, the amplifier circuit amplifies an input analog signal double. The input difference circuit calculates a difference between an output of the amplifier circuit and an output of the D/A converting circuit. By switching between the two switches, any one of an input analog signal and an output of the input difference circuit is selected and is input to the A/D converting circuit and the amplifier circuit.
In the A/D converter, an output of the input difference circuit that is sampled in a given cycle is input to the A/D converting circuit and the amplifier circuit in the next cycle such that the output is recursively converted in the A/D converting circuit. As a result, values of each bit can be acquired in order from the highest-order bit with repeated cycle processing. Accordingly, the A/D converter that converts an input analog signal into a digital signal having a number of bits, which is represented by the product of N and the number of bits of the A/D converting circuit, by repeating cycle processing N times (“N” represents an integer of 2 or more) can be configured.
As described above, in the general cyclic A/D converter, the resolution can be easily improved by increasing the number of cycle processing. However, an error generated in a given cycle is amplified double in the next cycle. That is, as the position of a bit including an error increases, the number of times the error is amplified increases, and the influence on a low-order bit increases. Accordingly, the resolution of the A/D converter is limited by an error generated from a high-order bit.
By sufficiently allocating a settling time required to settle the voltage a signal input to the A/D converter during the sampling of the signal, an error generated in each cycle can be reduced. As a result, the resolution of the A/D converter can be improved. However, in the general cyclic A/D converter, the periods of cycle processing are the same. Therefore, by increasing the settling time, the period of cycle processing also increases, and a total A/D conversion time required to complete A/D conversion increases. An increase in the A/D conversion time also leads to an increase in power consumption.
Thus, the improvement of the resolution of the A/D converter and a reduction in A/D conversion time have a trade-off relationship. Accordingly, it is difficult to simultaneously realize the improvement of the resolution of the A/D converter and a reduction in A/D conversion time.